1. Field of the Invention
The present invention relates generally to a wafer processing apparatus and method of use. It relates more particularly to a wafer processing apparatus including a mechanism for rotating a wafer in order to transfer heat to or from the wafer in a uniform manner.
2. Description of the Related Art
The terms “patterning means” or “patterning structure” as will be employed herein should be broadly interpreted to refer to means that can be used to endow an incoming radiation beam with a patterned cross-section, corresponding to a pattern that is to be created in a target portion of the substrate. The term “light valve” may also be used in this context. Generally, the pattern will correspond to a particular functional layer in a device being created in the target portion, such as an integrated circuit or other device (see below). Examples of such patterning means include:                (a) a mask: the concept of a mask is well known in lithography, and it includes mask types such as binary, alternating phase-shift, and attenuated phase-shift, as well as various hybrid mask types. Placement of such a mask in the radiation beam causes selective transmission (in the case of a transmissive mask) or reflection (in the case of a reflective mask) of the radiation impinging on the mask, according to the pattern on the mask. In the case of a mask, the support structure will generally be a mask table, which ensures that the mask can be held at a desired position in the incoming radiation beam, and that it can be moved relative to the beam if so desired;        (b) a programmable mirror array: an example of such a device is a matrix-addressable surface having a viscoelastic control layer and a reflective surface. The basic principle behind such an apparatus is that (for example) addressed areas of the reflective surface reflect incident light as diffracted light, whereas unaddressed areas reflect incident light as undiffracted light. Using an appropriate filter, the said undiffracted light can be filtered out of the reflected beam, leaving only the diffracted light behind; in this manner, the beam becomes patterned according to the addressing pattern of the matrix-addressable surface. The required matrix addressing can be performed using suitable electronic means. More information on such mirror arrays can be gleaned, for example, from U.S. Pat. Nos. 5,296,891 and 5,523,193, which are incorporated herein by reference. In the case of a programmable mirror array, the said support structure may be embodied as a frame or table, for example, which may be fixed or movable as required; and        (c) a programmable LCD array: an example of such a construction is given in U.S. Pat. No. 5,229,872, which is incorporated herein by reference. As above, the support structure in this case may be embodied as a frame or table, for example, which may be fixed or movable as required.        
For purposes of simplicity, the rest of this text may, at certain locations, specifically direct itself to examples involving a mask and mask table; however, the general principles discussed in such instances should be seen in the broader context of the patterning means as set forth above. Also, the projection system may hereinafter be referred to as the “lens”; however, this term should be broadly interpreted as encompassing various types of projection system, including refractive optics, reflective optics, and catadioptric systems, for example. The radiation system may also include components operating according to any of these design types for directing, shaping or controlling the projection beam of radiation, and such components may also be referred to below, collectively or singularly, as a “lens”.
Lithographic exposure apparatuses can be used, for example, in the manufacture of integrated circuits (ICs). In such a case, the patterning means may generate a circuit pattern corresponding to an individual layer of the IC, and this pattern can be imaged onto a target portion (e.g. comprising one or more dies) on a substrate (silicon wafer) that has been coated with a layer of radiation-sensitive material (resist). In general, a single wafer will contain a whole network of adjacent target portions that are successively irradiated via the projection system, one at a time.
In current apparatuses, employing patterning by a mask on a mask table, a distinction can be made between two different types of machine. In one type of lithographic exposure apparatus, each target portion is irradiated by exposing the entire mask pattern onto the target portion in one go; such an apparatus is commonly referred to as a wafer stepper. In an alternative apparatus—commonly referred to as a step-and-scan apparatus—each target portion is irradiated by progressively scanning the mask pattern under the projection beam in a given reference direction (the “scanning” direction) while synchronously scanning the substrate table parallel or anti-parallel to this direction. Because, in general, the projection system will have a magnification factor M (generally <1), the speed V at which the substrate table is scanned will be a factor M times that at which the mask table is scanned. More information with regard to lithographic devices as here described can be gleaned, for example, from U.S. Pat. No. 6,046,792, incorporated herein by reference.
It is to be noted that the lithographic apparatus may also be of a type having two or more substrate tables (and/or two or more mask tables). In such “multiple stage” devices the additional tables may be used in parallel, or preparatory steps may be carried out on one or more tables while one or more other tables are being used for exposures. Twin stage lithographic apparatus are described, for example, in U.S. Pat. No. 5,969,441 and WO 98/40791, incorporated herein by reference.
In manufacturing processes employing lithographic exposure apparatuses a pattern (e.g. in a mask or reticle) is imaged or exposed onto a substrate wafer that is at least partially covered by a layer of radiation-sensitive material (resist). Prior to this exposure step, the substrate wafer may undergo various processes, such as priming, resist coating, and a soft bake.
After exposure, the substrate may be subjected to additional processes, such as a post-exposure bake (PEB), chilling, development, a hard bake and measurement/inspection of the imaged features. These post-exposure processes are used as a basis to pattern an individual layer of a device, e.g. an IC. Such a patterned layer may then undergo further post-exposure processes such as etching, ion-implantation (doping), metallization, oxidation, chemo-mechanical polishing, etc., all intended to finish off an individual layer. If several layers are required, then the entire procedure, or a variant thereof, will have to be repeated for each new layer.
As described above, there are generally multiple operations (PEB, hard bake) that involve raising the temperature of a wafer, for example, in order to hasten the setting of a layer of photoresist. Bake operations are generally performed using a plate-like structure that includes one or more heating elements, generally known as a bake plate. The wafer to be processed is held in proximity to, or directly on, the bake plate. In some cases, it may also become necessary or desirable to quickly and uniformly chill the heated wafer to an ambient temperature so that the wafer will not introduce thermal contamination to other equipment in the production process. For this purpose, a chill plate is used.
Combination bake/chill stations have been described, for example, in U.S. Pat. Nos. 5,431,700 and 6,307,184. In these devices, a heating element and a cooling element are disposed in close proximity so that no external robot is required to move the wafer under treatment from one station to another.
Eventually, an array of devices will be present on the substrate (wafer) and these devices are then separated from one another by a technique such as dicing or sawing, whence the individual devices can be mounted on a carrier, connected to pins, etc. Further information regarding such processes can be obtained, for example, from the book “Microchip Fabrication: A Practical Guide to Semiconductor Processing”, Third Edition, by Peter van Zant, McGraw Hill Publishing Co., 1997, ISBN 0-07-067250-4, incorporated herein by reference.
Needless to say, it is important that the features and profile of the pattern exposed on the target fields of the wafer substrate are replicated as accurately as possible. To this end, manufacturers normally specify the critical dimension (CD) of the exposed pattern in order to characterize the features and profile of the pattern and establish a benchmark level of quality and uniformity. Another important consideration is the ability to manipulate the lithographic fabrication process to repeatedly and increasingly yield high-quality substrate wafers.
There are, however, numerous activities during the lithographic fabrication process that affect the critical dimension uniformity (CDU) and compromise the quality of the exposed patterns. Indeed, the very pre- and post-exposure processes that service and treat the substrate wafers may contribute to variations in the CDU. Moreover many of these pre- and post-exposure processes involve the use of chemicals that react with the substrate wafers to achieve an intended effect on the wafer. And, although these chemical reactions may follow predictable Arrhenius behaviors (i.e., reaction rates are a function of temperature), temperature gradients may not be well controlled as the reactions occur. All these factors may contribute to variations and non-uniformities in either the individual target fields, across a wafer, or between wafers—ultimately resulting in loss of productive yields.